This invention relates to a digital phase-locked loop (PLL) circuit and, more particularly, to a digital PLL circuit in which an edge position of the input signal waveform is detected and the PLL operation is performed in a digital fashion based on the detected edge position.
In general, the PLL circuit is a phase synchronizing circuit in which the phase of an input signal follows the phase of a reference signal. An analog PLL circuit is made up of a phase comparator, a low-pass filter and a voltage-control led oscillator. Recently, there has been proposed a digital PLL circuit in which the operation of the analog PLL circuit is performed in a digital fashion.
With the digital PLL circuit, the phase difference between the PLL output signal and the input signal is measured using a master clock. That is, the phase difference between the edge of the input signal and the output clock of the PLL circuit is found by the master clock. Based on such phase difference, the output clock is controlled so as to be in phase with the input clock. A precision at least a factor of two higher than the bit clock of the input signal is required on the master clock. As the clock frequency of the input signal is increased, it becomes increasingly difficult to obtain a master clock frequency so as to be higher by at least a factor of two because the operating clock frequency cannot be increased without limitations. Thus a digital PLL circuit which facilitates phase difference detection without employing a higher frequency of the master clock is desirable . In a digital PLL circuit, the input signals are sampled with the master clocks. The timing of the input signal edge, produced by such sampling, contains an error dependent on the master clocks. Therefore, for inhibiting data errors in the PLL circuit, it is necessary to sample the input signal with a master clock having as short a period as possible to capture the timing of the input signal edge accurately. Recently, despite limitations imposed on the master clock frequency because of semiconductor process constraints a PLL circuit has been desired in which a satisfactory error rate may be assured even if the ratio Of the master clock frequency/PLL output clock frequency is on the order of 2 or higher.
The present inventors have disclosed in Application SHO 62-127168 (JP Patent Publication KOKAI No. 63-292825) a technique in which the time duration of a number N of output clock pulses of PLL circuit is detected using a master clock having a predetermined frequency and the time duration is multiplied by 1/N to find the period of the PLL clock with a degree of precision equal to N times the master clock.
According to the teaching of the Application No. SHO 62-175732 (JP Patent KOKAI Publication No. 64-19826), the time duration of N/K number of output clock pulses of the PLL circuit is sequentially detected and the K number of the sequentially detected time durations is multiplied by 1/N to find the output clock period. By these techniques, the digital PLL is formed using master clocks of a lower frequency.
Recently, the output PLL clock frequency (reproducing clock frequency ) has been increased in keeping up with higher system performance and a demand for master clock frequency to PLL output clock frequency ratio on the order of 2 to 3. Since the error rate tends to be increased with the above techniques, further improvement is desired.